An ADCP digital echo signal processing system based on SoC FPGA

The proposed acoustic Doppler current profiler (ADCP) digital echo signal processing system based on system on chip field programmable gate array (SoC FPGA) is designed to meet the requirements of miniaturization and high real-time signal processing for ADCP. Based on the parallel data processing capability of FPGA, the intermediate frequency (IF) orthogonal sampling method using polyphase decomposition is employed to generate the echo complex signal atthe programmable logic (PL) end. Furthermore, complex correlation calculation is performed to obtain the correlation function, correlation energy, and position of maximum correlation energy point in the echo signal. Finally, frequency shift calculation is carried out in the processor system (PS). Experimental results demonstrate that this approach achieves fast echo signal processing speed at PL terminal with good real-time and high accuracy.